• Added support for BSIMIMG 103.1.0.
  
• Changes made to the Gnode DC solver. The finishing small conductance (GnodeFinal) has been reduced, from 1e-12 to 1.0e 1e -18. Other changes prevent the continuation from getting stuck at the smaller values. Where the results are different, we find that the solution is nearly always more accurate, and may be a little slower. The type of circuits that this affects are typically back-to-back PN junctions, like SOI.
  

• Upgraded OpenAccess to version 22.61p022.
  
• (Beta release) Added preference to enable the Keysight Caranu Theme, which includes a dark mode.
  
• Python API Updates:
  

• Resource settings for Design Cloud can be set as constructor parameters. Read the Python API documentation for detailed usage.
  
• String Enums for Design Cloud job status. While querying Design Cloud job status, we return StrEnum instead of str. Read the Python API documentation for detailed usage.
  
• Validate memory and threads before being passed to SiteCluster during job submission.
  
• Support for Design Cloud simulations has been added to Queue Manager, ensuring sequential testbench execution and following all other standard Queue Manager behaviors.
  

• Users can now access individual Harmonic Balance OutFiles for each subjob in the expected location within the Design Cloud simulation. When an OutFile is specified for Harmonic Balance (e.g., HBFinalSolution) and a parallel job with 3 subjobs is run, each subjob's individual HB OutFiles will be installed in the workspace's data directory. The files will be named in the format: HBFinalSolution_j0, HBFinalSolution_j1, and HBFinalSolution_j2.
  
• Warn about variables with unknown values for Hb output file Paths during the netskimming stage, resulting in skipped installation of such output files.
  
• During HPC cloud circuit simulation, support has been added for DAC files referenced by the main DAC discrete file that are located outside the shared root and workspace.
  
• During HPC cloud circuit simulation, a warning is now generated for variables with unknown values in HB output file paths, notifying users where output files with paths containing these variables can be found.
  

• The 'Show Physical Connectivity' feature has been enhanced to support smart mount instances. For more information, refer to Highlighting Connectivity.
  
• The multilayer stacked line type definition has been enhanced to support keepouts. This allows users to draw keepouts on different layers alongside traces that use these line types.
  
• The display of coordinate locations for overlap zones has been improved and synchronized across various GUIs, including 'Check Designs' and 'Resolve Overlap Zone Conflicts'. For more information, refer to Net Overlap Zone and Design Synchronization.
  
• The AEL functions db_get_plane_degas_options_minimum_venting_area and db_set_plane_degas_options_minimum_venting_area now require a design context.
  
• The appObject Iterator related AEL APIs have been added as below:
  

• The Copy/Paste functionality has been enhanced to retain font and size annotations for components.
  
• The Property Editor has been enhanced to support the editing of interconnect segments.
  
• "Force to Grid" command has been enhanced to support keepout objects.
  
• Added user preference to display rounded numeric parameters to a given decimal place. This preference only affects display of parameters in the schematic window and Edit Parameter dialog. It does not affect simulation or layout artwork. This preference can be found in both layout and schematic's preferences by going to Options → Preferences → Display → Parameter Display. This option is enabled by default to the 12th decimal place.
  
• Deprecated legacy ground components in layout ("ads_rflib:GROUND:layout"). Layouts with these components will be automatically updated to use ground markers instead, and the legacy ground components in the design will be automatically removed. Nets will not change as a result of this deprecation.
  

• The AEL APIs for GDSII translator are now workable in the automation mode.
  
• The AEL APIs for DXF/DWG and Gerber export translators are now workable in the automation mode.
  
• ODB++ Importer resolution for processing shapes has been increased to 10,000 points/mm to improve dimensional accuracy.
  

• The multi-threading of the direct dense matrix load has been improved, giving a speedup in the range of 5% to 30%.
  
• The 'Delta Gap' and 'Closed loop' feed type is now supported for horizontal multi-pin component port definitions.
  

• The Python version in RFPro 2026 has been upgraded to Python 3.13. There are no significant backward compatibility issues, except for the removal of deprecated standard libraries. Python scripts from RFPro 2025 should still work in RFPro 2026 unmodified. For more information on what's changed in Python 3.13 and what libraries have been removed, see

  Idézet:A kódrészlet megtekintéséhez be kell jelentkezned, vagy nincs jogosultságod a tartalom megtekintéséhez.

  . RFPro 2026 does not enable the experimental free-threaded mode or Just-In-Time compiler.
  
• The metal bias options are now part of the Python script generated by selecting the 'Create script' menu.
  
• RFPro simulations now provide the 'job-version' sitecluster arguments.
  
• A new Python function has been added to export the far field to an .ffio file given an excitation and optionally a frequency list.
  
• The automatic conversion from Python 2 scripts to Python 3 has been removed from ADS RFPro 2026. Python 3 was first introduced in ADS RFPro 2021, and scripts could automatically be converted to Python 2 when opening older projects. This is no longer supported since the introduction of Python 3.13 in ADS 2026. If you still wish to automatically convert older projects, you can open them in ADS 2025 and resave them with the converted scripts.
  

• Supports LPDDR6 in Memory Designer.
  
• Supports HBM3 Enhanced data rates in Memory Designer.
  
• Supports PAM-n statistical simulation for GDDR7 in Memory Designer.
  
• Enhanced Mask features:
  

• Supports PCIe Gen7 in System Designer for PCIe.
  
• Supports SIPro cell sweep in System Designer for PCIe and USB.
  
• Supports Pathfinding mode in System Designer for PCIe and USB.
  
• Enhanced name parsing in System Designer for PCIe and USB.
  
• Improved AMI model builder:
  

• The Python version in SIPro/PIPro 2026 has been upgraded to Python 3.13. There are no significant backward compatibility issues, except for deprecated standard libraries that have been removed. Python scripts from SIPro/PIPro 2025 should still work in SIPro/PIPro 2026 unmodified. For more information on changes in Python 3.13, and removed libraries, see

  Idézet:A kódrészlet megtekintéséhez be kell jelentkezned, vagy nincs jogosultságod a tartalom megtekintéséhez.

  . SIPro/PIPro 2026 does not enable the experimental free-threaded mode or Just-In-Time compiler.
  
• The automatic conversion from Python 2 scripts to Python 3 has been removed from ADS SIPro/PIPro 2026. Python 3 was first introduced in ADS SIPro/PIPro 2021, and scripts could automatically be converted to Python 3 when opening older projects. This is no longer supported since the introduction of Python 3.13 in ADS 2026. To automatically convert older projects, you can open them in ADS 2023 and resave them with the converted scripts.
  
• The BRD importer requires Allegro PCB Designer version 23.1-2023-S009 or newer.
  
• Projects saved in ADS 2026 cannot be opened in older versions.
  

• Added a linear magnetic core model, which supports frequency-dependent complex relative permeability.
  
• Introduced a new palette "Power Sources" including VtClock, VtConst, VtPulsePE, VtStepRamp, and VtTriangular.
  

• Added support for the E/G element in PSpice netlists using the TABLE keyword in VALUE expressions.
  
• Corrected node rename inconsistencies during import.
  

• The Python version in QuantumPro 2026 has been upgraded to Python 3.13. There are no significant backward compatibility issues, except for deprecated standard libraries that have been removed. Python scripts from QuantumPro 2025 should still work in QuantumPro 2026 unmodified. For more information on what's changed in Python 3.13, and what libraries have been removed, see

  Idézet:A kódrészlet megtekintéséhez be kell jelentkezned, vagy nincs jogosultságod a tartalom megtekintéséhez.

  . QuantumPro 2026 does not enable the experimental free-threaded mode or Just-In-Time compiler.
  
• Enabled copy/paste functionality for Extracted Quantum Parameters.
  
• Enhanced the Single Qubit Design Flow example to demonstrate time dynamics using the newly introduced Time Dynamics Analysis feature in Quantum Tools.
  
• Updated the Superconducting Resonator with Kinetic Inductance design flow example to include circuit modeling using the newly introduced superconducting CPW components.
  

• Quantum parameters are now automatically logged in a JSON file.
  
• Enabled specification of EMPro materials directly within QuantumPro, allowing users to assign anisotropic dielectric materials to the substrate.
  
• Enhanced frequency-domain parameter extraction to continue processing even when some qubits fail to extract, with improved error messages that provide diagnostics for each failed qubit.
  

• Added SupercondCPWSub to the ADS Circuit environment, enabling modeling of superconducting coplanar waveguide circuits.
  
• Added Flux and Zero-Pi qubits to the library of qubits available for Hamiltonian analysis.
  

• Added a palette for quantum system components in the ADS Circuit environment.
  
• Introduced a new quantum tool in the circuit environment to support the design and analysis of dilution fridge input lines.
  
• Introduced Time Dynamics Analysis to the quantum tools in the ADS circuit environment, enabling users to simulate and observe the time-domain behavior of quantum chips using extracted quantum parameters.
  

• Solved Python execution failure that could occur when importing keysight.ads.dds on Linux in automation mode.
  
• Fixed issues with deactivated Python equations when opening Data Display.
  
• Fixed a crash when using Python custom context menus.
  

• Fixed an issue related to incorrect signedness of the Keepout element's purposeNum attribute in ABL-it is now correctly treated as a signed integer as declared in the ABL schema.
  
• Implemented new AEL functions that regenerate OA shape data using desired arc resolution, see: de_regenerate_oa_shapes_from_control_data() and de_regenerate_design_oa_shapes_from_control_data().
  

• The 'Closed loop' feed type algorithm has been refined to not cause feed lines to overlap.
  
• In case of an edge pin on a thick conductor, the current will be injected through the vertical cell connected to the edge rather than the horizontal one, yielding a more accurate DC resistance.
  

• On Windows 11 24h2, SentinelOne antivirus may prevent the different xxPro environments from starting properly. As a workaround, disable SentinelOne or add path exclusions for the ADS installation.
  
• A bug in the RFPro-FEM simulator has been fixed that could lead to a wrong height of the pin location in a complex assembly.
  
• A bug has been fixed that could lead to an 'Unexpected Condition' during a copy/paste operation of a frequency plan.
  

• Fixed a bug in Memory Designer where the DQ and DM mask sizes showed different values.
  
• Fixed a bug in Memory Designer where the DIMM connector could not update signal information from a saved CSV configuration file.
  
• Fixed a bug in Memory Designer where ADS crashed when the mask width or height was 0 or negative.
  

• Fixed a bug where an IBIS file located in a remote location couldn't be read during simulation.
  
• Fixed a bug in the S-Parameter Toolkit where port values were swapped when using Enable Port Reduction.
  
• Fixed a bug in S-parameter toolkit where changes to the reference impedance were not reflected under Enable Port Reduction.
  

Idézet:A kódrészlet megtekintéséhez be kell jelentkezned, vagy nincs jogosultságod a tartalom megtekintéséhez.